The ________ can be turned off by the CPU before the execution of critical instruction sequences that must not be interrupted.

Similar Questions

1. How does the software trigger an interrupt?

A. Sending signals to CPU through bus B. Executing a special operation called system call C. Executing a special program called system program D. Executing a special program called interrupt trigger program

2. What is a trap/exception?

A. hardware generated interrupt caused by an error B. software generated interrupt caused by an error C. user generated interrupt caused by an error D. none of the mentioned

3. What is an ISR?

A. Information Service Request B. Interrupt Service Request C. Interrupt Service Routine D. Information Service Routine

4. What is an interrupt vector?

A. It is an address that is indexed to an interrupt handler B. It is a unique device number that is indexed by an address C. It is a unique identity given to an interrupt D. None of the mentioned

5. DMA is used for __________

A. High speed devices B. Low speed devices C. Utilizing CPU cycles D. All of the mentioned

6. In a memory mapped input/output __________

A. the CPU uses polling to watch the control bit constantly, looping to see if a device is ready B. the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available C. the CPU receives an interrupt when the device is ready for the next byte D. the CPU runs a user written code and does accordingly

7. In a programmed input/output(PIO) __________

A. the CPU uses polling to watch the control bit constantly, looping to see if a device is ready B. the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available C. the CPU receives an interrupt when the device is ready for the next byte D. the CPU runs a user written code and does accordingly

8. In an interrupt driven input/output __________

A. the CPU uses polling to watch the control bit constantly, looping to see if a device is ready B. the CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available C. the CPU receives an interrupt when the device is ready for the next byte D. the CPU runs a user written code and does accordingly

9. How does the Hardware trigger an interrupt?

A. Sending signals to CPU through a system bus B. Executing a special program called interrupt program C. Executing a special program called system program D. Executing a special operation called system call

10. Which operation is performed by an interrupt handler?

A. Saving the current state of the system B. Loading the interrupt handling code and executing it C. Once done handling, bringing back the system to the original state it was before the interrupt occurred D. All of the mentioned