Q.
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1”=the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
Similar Questions
1.
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register
2. In a sequential circuit the next state is determined by ________ and _______
3. The divide-by-60 counter in digital clock is implemented by using two cascading counters:
4. In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
5. The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of
the flip-flop.
6. 74HC163 has two enable input pins which are _______ and _________
7. ____________ is said to occur when multiple internal variables change due to change in one input variable
8. The _____________ input overrides the ________ input
9. A decade counter is __________.
10. In asynchronous transmission when the transmission line is idle, _________
DIGITAL LOGIC DESIGN TOPICS